drivers: i3c: cadence: fix tx_fifo width for target mode on rev_id 1p7

[naveeng1001]

Cadence I3C target FIFO width has been increased to 4 bytes in i3c hardware rev_id 1p7. Writing 1 byte to 4 byte FIFOs can cause unintentional padding for bytes written from TX threshold interrupt handler. Fixed the target callback to handle tx width of i3c target writes to FIFO, by using run time rev_id check.

[github-actions]

Hello @naveeng1001, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
If you are stuck or need help please join us on Discord and ask your question there. Additionally, you can escalate the review when applicable. 😊

[github-actions]

Hi @naveeng1001!
Congratulations on getting your very first Zephyr pull request merged 🎉🥳. This is a fantastic achievement, and we're thrilled to have you as part of our community!

To celebrate this milestone and showcase your contribution, we'd love to award you the Zephyr Technical Contributor badge. If you're interested, please claim your badge by filling out this form: Claim Your Zephyr Badge.

Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁