Fix for testbenches with >32 ports

v0.1-rc12

Step.cpp: fix 32bit/64bit issue

truncate large traces when rendering

v0.1-rc10

Trace: truncate large traces when rendering them (including diffs for…

alpha - rc9

extend to support 64 ports in traces (instead of 32)

alpha - rc8

Fix missing include for 'ceil' in Trace

TraceBuilder::signal() - add support for std::vector<uint32_t>

v0.1-rc7

TraceBuilder: signal() - add support for vector<uint32_t>

alpha - rc6

separate simulation of combinatorial logic and sequential logic

alpha - rc5

TestBench: add onStepSimulate() - opportunity to simulate input values with correct clock setting

alpha - rc4

TestBench::step() - eval() the core to settle combinatorial values before inverting i_clk, and evaluating again

alpha - rc3

TestBench - support setting clock polarity
TestBench - rename 'nextStep' as 'step'

alpha - rc2

v0.1-rc2

rename BUILD file + update .gitignore