Fix a lot of xprop and add boot mem init

src/main/scala/vexiiriscv/Param.scala

@@ -118,6 +118,7 @@ class ParamSimple(){
   var embeddedJtagInstruction = false
   var embeddedJtagCd: ClockDomain = null
   var embeddedJtagNoTapCd: ClockDomain = null
+  var bootMemClear = false
 
   def fetchMemDataWidth = 32*decoders max fetchMemDataWidthMin
   def lsuMemDataWidth = xlen max lsuMemDataWidthMin
@@ -321,6 +322,7 @@ class ParamSimple(){
     opt[Int] ("debug-triggers") action { (v, c) => privParam.debugTriggers = v }
     opt[Unit]("debug-triggers-lsu") action { (v, c) => privParam.debugTriggersLsu = true }
     opt[Unit]("debug-jtag-tap") action { (v, c) => embeddedJtagTap = true }
+    opt[Unit]("with-boot-mem-init") action { (v, c) => bootMemClear = true }
   }
 
   def plugins(hartId : Int = 0) = pluginsArea(hartId).plugins
@@ -353,7 +355,8 @@ class ParamSimple(){
         hashWidth = btbHashWidth,
         readAt = 0,
         hitAt = 1,
-        jumpAt = 1+relaxedBtb.toInt
+        jumpAt = 1+relaxedBtb.toInt,
+        bootMemClear = bootMemClear
       )
 //      plugins += new prediction.DecodePredictionPlugin(
 //        decodeAt = decoderAt,
@@ -364,7 +367,8 @@ class ParamSimple(){
       plugins += new prediction.GSharePlugin (
         memBytes = 4 KiB,
         historyWidth = 12,
-        readAt = 0
+        readAt = 0,
+        bootMemClear = bootMemClear
       )
       plugins += new prediction.HistoryPlugin()
     }
@@ -414,6 +418,7 @@ class ParamSimple(){
       reducedBankWidth = fetchL1ReducedBank,
       hitsWithTranslationWays = true,
       tagsReadAsync = false,
+      bootMemClear = bootMemClear,
       translationStorageParameter = MmuStorageParameter(
         levels = List(
           MmuStorageLevel(
@@ -561,7 +566,8 @@ class ParamSimple(){
         setCount       = lsuL1Sets,
         wayCount       = lsuL1Ways,
         withBypass     = withLsuBypass,
-        withCoherency  = lsuL1Coherency
+        withCoherency  = lsuL1Coherency,
+        bootMemClear = bootMemClear
       )
     }
 

src/main/scala/vexiiriscv/execute/fpu/FpuAddSharedPlugin.scala

@@ -97,7 +97,9 @@ class FpuAddSharedPlugin(lane: ExecuteLanePlugin,
       Decode.UOP_ID := reader(_.uopId)
       valid := reader.oh.orR
       val GROUP_OH = Payload(Bits(uopsAt.size bits))
-      assert(CountOne(GROUP_OH) <= 1)
+      when(isValid) {
+        assert(CountOne(GROUP_OH) <= 1)
+      }
       for ((at, sel) <- (uopsAt.keys, GROUP_OH.asBools).zipped) {
         sel := (for (port <- ports; (portAt, i) <- port.cmd.ats.zipWithIndex; if portAt == at) yield port.cmd.at(i)).orR
       }

src/main/scala/vexiiriscv/execute/fpu/FpuUnpackerPlugin.scala

@@ -10,6 +10,8 @@ import vexiiriscv.decode.Decode
 import vexiiriscv.execute._
 import vexiiriscv.riscv._
 import FpuUtils._
+import vexiiriscv.Global.TRAP
+
 import scala.collection.mutable
 import scala.collection.mutable.ArrayBuffer
 
@@ -171,7 +173,7 @@ class FpuUnpackerPlugin(val layer : LaneLayer, unpackAt : Int = 0, packAt : Int
           mantissaWidth = Riscv.fpuMantissaWidth
         ))
 
-        val unpackerSel = isValid && up(rfa.ENABLE) && rfa.is(FloatRegFile, rfa.RFID) //A bit pessimistic, as not all float instruction will need unpacking
+        val unpackerSel = isValid && up(rfa.ENABLE) && rfa.is(FloatRegFile, rfa.RFID) && !up(TRAP) //A bit pessimistic, as not all float instruction will need unpacking
 
         val f32 = new Area {
           val mantissa = input(0, 23 bits).asUInt

src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala

@@ -93,9 +93,10 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
                   var withCoherency: Boolean = false,
                   var withBypass: Boolean = false,
                   var probeIdWidth: Int = -1,
-                  var ackIdWidth: Int = -1) extends FiberPlugin with InitService with LsuL1Service{
+                  var ackIdWidth: Int = -1,
+                  var bootMemClear : Boolean) extends FiberPlugin with InitService with LsuL1Service{
 
-  override def initHold(): Bool = !logic.initializer.done
+  override def initHold(): Bool = !logic.initializer.done || bootMemClear.mux(logic.initializerMem.busy, False)
 
   def memParameter = LsuL1BusParameter(
     addressWidth = Global.PHYSICAL_WIDTH,
@@ -885,7 +886,9 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
         WAIT_REFILL := refillHazards | refill.free.orMask(refill.full).andMask(!HAZARD && (askRefill || askUpgrade))
         WAIT_WRITEBACK := 0 // TODO  // writebackHazards | writeback.free.andMask(askRefill && refillWayNeedWriteback)
 
-        assert(CountOne(Cat(askRefill, doUpgrade, doFlush)) < 2)
+        when(SEL) {
+          assert(CountOne(Cat(askRefill, doUpgrade, doFlush)) < 2)
+        }
 
         when(SEL) {
           shared.write.address := MIXED_ADDRESS(lineRange)
@@ -1149,6 +1152,17 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
       }
     }
 
+    val initializerMem = bootMemClear generate new Area {
+      val counter = Reg(UInt(log2Up(bankWordCount) + 1 bits)) init (0)
+      val busy = !counter.msb
+      when(busy) {
+        counter := counter + 1
+        banksWrite.mask.setAll()
+        banksWrite.address := counter.resized
+        banksWrite.writeData.clearAll()
+        banksWrite.writeMask.setAll()
+      }
+    }
 
     if(withCoherency) c.pip.build()
     tagsWriteArbiter.build()

src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala

@@ -65,7 +65,8 @@ class FetchL1Plugin(var translationStorageParameter: Any,
                     var ctrlAt: Int = 2,
                     var hitsWithTranslationWays: Boolean = false,
                     var reducedBankWidth: Boolean = false,
-                    var tagsReadAsync: Boolean = false) extends FiberPlugin with FetchL1Service with InitService {
+                    var tagsReadAsync: Boolean = false,
+                    var bootMemClear : Boolean) extends FiberPlugin with FetchL1Service with InitService {
 
   def getBusParameter() = FetchL1BusParam(
     physicalWidth = PHYSICAL_WIDTH,
@@ -75,7 +76,7 @@ class FetchL1Plugin(var translationStorageParameter: Any,
   )
 
 
-  override def initHold(): Bool = logic.invalidate.firstEver
+  override def initHold(): Bool = logic.invalidate.firstEver || bootMemClear.mux(logic.initializer.busy, False)
 
   val logic = during setup new Area{
     val pp = host[FetchPipelinePlugin]
@@ -493,6 +494,19 @@ class FetchL1Plugin(var translationStorageParameter: Any,
       plru.write.data.clearAll()
     }
 
+    val initializer = bootMemClear generate new Area {
+      val counter = Reg(UInt(log2Up(banks(0).mem.wordCount) + 1 bits)) init (0)
+      val busy = !counter.msb
+      when(busy) {
+        counter := counter + 1
+        for (bank <- banks; port = bank.write) {
+          port.valid := True
+          port.address := counter.resized
+          port.data := 0
+        }
+      }
+    }
+
     buildBefore.release()
   }
 

src/main/scala/vexiiriscv/prediction/BtbPlugin.scala

@@ -8,7 +8,7 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.misc.plugin.FiberPlugin
 import spinal.lib.misc.pipeline._
-import vexiiriscv.fetch.{Fetch, FetchPipelinePlugin, PcService}
+import vexiiriscv.fetch.{Fetch, FetchPipelinePlugin, InitService, PcService}
 import Fetch._
 import vexiiriscv.Global._
 import vexiiriscv.schedule.{DispatchPlugin, ReschedulePlugin}
@@ -25,13 +25,16 @@ class BtbPlugin(var sets : Int,
                 var hashWidth : Int = 16,
                 var readAt : Int = 0,
                 var hitAt : Int = 1,
-                var jumpAt : Int = 1) extends FiberPlugin with FetchWordPrediction {
+                var jumpAt : Int = 1,
+                var bootMemClear : Boolean) extends FiberPlugin with FetchWordPrediction with InitService  {
 
 
   override def useAccurateHistory: Boolean = jumpAt == 1
 
   def chunksRange = 0 until chunks
 
+  override def initHold(): Bool = bootMemClear.mux(logic.initializer.busy, False)
+
   val logic = during setup new Area{
     val fpp = host[FetchPipelinePlugin]
     val pcp = host[PcService]
@@ -269,6 +272,30 @@ class BtbPlugin(var sets : Int,
         }
       }
     }
+
+    val initializer = bootMemClear generate new Area {
+      val counter = Reg(UInt(log2Up(sets max rasDepth) + 1 bits)) init (0)
+      val busy = !counter.msb
+      when(busy) {
+        counter := counter + 1
+        onLearn.port.valid := True
+        onLearn.port.address := counter.resized
+        for (data <- onLearn.port.data) {
+          data.hash.setAll
+          data.sliceLow := 0
+          data.isBranch := False
+          data.isPush := False
+          data.isPop := False
+          if (!withCondPrediction) data.taken := False
+        }
+
+        if (withRas) {
+          ras.write.valid := True
+          ras.write.address := counter.resized
+          ras.write.data := 0
+        }
+      }
+    }
     buildBefore.release()
   }
 }

src/main/scala/vexiiriscv/prediction/GSharePlugin.scala

@@ -4,7 +4,7 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.misc.plugin.FiberPlugin
 import spinal.lib.misc.pipeline._
-import vexiiriscv.fetch.{Fetch, FetchPipelinePlugin, PcService}
+import vexiiriscv.fetch.{Fetch, FetchPipelinePlugin, InitService, PcService}
 import Fetch._
 import vexiiriscv.Global._
 import vexiiriscv.schedule.{DispatchPlugin, ReschedulePlugin}
@@ -20,11 +20,13 @@ class GSharePlugin(var historyWidth : Int,
                    var memBytes : BigInt = null,
                    var readAt : Int = 0,
                    var counterWidth : Int = 2,
-                   var readAsync : Boolean = false) extends FiberPlugin with FetchConditionalPrediction with HistoryUser{
+                   var readAsync : Boolean = false,
+                   var bootMemClear: Boolean) extends FiberPlugin with FetchConditionalPrediction with HistoryUser with InitService {
 
   override def useHistoryAt = readAt
   override def historyWidthUsed = historyWidth
   override def getPredictionAt(stageId: Int) = host[FetchPipelinePlugin].fetch(stageId)(GSHARE_COUNTER).map(_.msb)
+  override def initHold(): Bool = bootMemClear.mux(logic.initializer.busy, False)
 
   val GSHARE_COUNTER = Payload(Vec.fill(SLICE_COUNT)(UInt(counterWidth bits)))
 
@@ -106,6 +108,17 @@ class GSharePlugin(var historyWidth : Int,
       mem.write.address := hash
       mem.write.data := updated
     }
+
+    val initializer = bootMemClear generate new Area {
+      val counter = Reg(UInt(log2Up(words) + 1 bits)) init (0)
+      val busy = !counter.msb
+      when(busy) {
+        counter := counter + 1
+        mem.write.valid := True
+        mem.write.address := counter.resized
+        mem.write.data.clearAll()
+      }
+    }
     buildBefore.release()
   }
 }

src/main/scala/vexiiriscv/soc/litex/Soc.scala

@@ -202,7 +202,7 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
 
 
     val patcher = Fiber build new AreaRoot {
-      val mBus = withMem generate Axi4SpecRenamer(master(mem.toAxi4.down.pipelined()))
+      val mBus = withMem generate Axi4SpecRenamer(master(mem.toAxi4.down.expendId(8).pipelined()))
       val pBus = AxiLite4SpecRenamer(master(
         vexiiParam.lsuL1Enable.mux(
           peripheral.toAxiLite4.down.pipelined(
@@ -665,7 +665,7 @@ TODO debug :
 [ 9576.286235] [<ffffffff80002f76>] ret_from_exception+0x0/0xc
 [ 9576.295073] [<ffffffff80144a98>] do_sys_poll+0x144/0x42c
 
-perf stat  --timeout 1000 -e r12,r13,r1a,r1b,stalled-cycles-frontend,stalled-cycles-backend,cycles,instructions,branch-misses,branches -p 532
+perf stat  --timeout 1000 -e r12,r13,r1a,r1b,stalled-cycles-frontend,stalled-cycles-backend,cycles,instructions,branch-misses,branches -p $!
 
 relaxed btb =>
 Startup finished in 9.108s (kernel) + 1min 17.848s (userspace) = 1min 26.956s
@@ -688,6 +688,18 @@ Startup finished in 8.219s (kernel) + 1min 5.727s (userspace) = 1min 13.946s
 graphical.target reached after 1min 4.705s in userspace.
 timed 5026 gametics in 8999 realtics (19.547728 fps
 
+16 KB i$d$ relaxed btb 64 bits bus
+Startup finished in 8.237s (kernel) + 1min 753ms (userspace) = 1min 8.991s
+graphical.target reached after 59.891s in userspace.
+timed 5026 gametics in 8943 realtics (19.670134 fps)
+
+16 KB i$d$ stressed btb 64 bits bus
+Startup finished in 8.806s (kernel) + 1min 213ms (userspace) = 1min 9.019s
+graphical.target reached after 59.298s in userspace.
+timed 5026 gametics in 8742 realtics (20.122398 fps)
+
+
+
 SLICE_X122Y49        FDRE (Prop_fdre_C_Q)         0.456    11.240 r  VexiiRiscvLitex_2f3ff2b95842595a3b7d75e26dfd301e/vexiis_1_logic_core/vexiis_1_logic_core_toplevel_execute_ctrl1_up_float_RS2_lane0_reg[52]/Q
                      net (fo=7, routed)           0.824    12.064    VexiiRiscvLitex_2f3ff2b95842595a3b7d75e26dfd301e/vexiis_1_logic_core/FpuUnpack_RS2_f64_exponent[0]
 SLICE_X133Y48        LUT3 (Prop_lut3_I0_O)        0.124    12.188 r  VexiiRiscvLitex_2f3ff2b95842595a3b7d75e26dfd301e/vexiis_1_logic_core/FpuAddSharedPlugin_logic_pip_node_1_inserter_rs2_exponent[4]_i_3__0/O