refractoring

src/main/scala/vexiiriscv/execute/BranchPlugin.scala

@@ -33,7 +33,7 @@ object BranchPlugin extends AreaObject {
 class PcCalc(bp: BranchPlugin, at: Int) extends Area {
   import bp._
   import BranchPlugin._
-  val ctrl = bp.layer.el.execute(at)
+  val ctrl = bp.layer.lane.execute(at)
   import ctrl._
 
   val srcp = host.find[SrcPlugin](_.layer == layer)
@@ -74,7 +74,7 @@ class BranchPlugin(val layer : LaneLayer,
   def catchMissaligned = !Riscv.RVC
   override def getLearnPort(): Option[Stream[LearnCmd]] = logic.jumpLogic.learn
 
-  def pluginsOnLane = host.list[BranchPlugin].filter(_.layer.el == layer.el)
+  def pluginsOnLane = host.list[BranchPlugin].filter(_.layer.lane == layer.lane)
   val pcCalc : Handle[PcCalc] = during build {
     // So, here we look for other branchplugins on the same lane to try reusing their calculation (better for fmax / LUT, cost some FF)
     val firstOfLane = pluginsOnLane.sortBy(_.jumpAt).head
@@ -86,7 +86,7 @@ class BranchPlugin(val layer : LaneLayer,
   }
 
   val logic = during setup new Logic{
-    val wbp = host.find[WriteBackPlugin](p => p.lane == layer.el && p.rf == IntRegFile)
+    val wbp = host.find[WriteBackPlugin](p => p.lane == layer.lane && p.rf == IntRegFile)
     val sp = host[ReschedulePlugin]
     val pcp = host[PcPlugin]
     val hp = host.get[HistoryPlugin]

src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala

@@ -42,7 +42,7 @@ class CsrAccessPlugin(val layer : LaneLayer,
   val logic = during setup new Area {
     val elp = host.find[ExecuteLanePlugin](_.laneName == layer.laneName)
     val irf = host.find[RegfileService](_.rfSpec == IntRegFile)
-    val iwb = host.find[IntFormatPlugin](_.lane == layer.el)
+    val iwb = host.find[IntFormatPlugin](_.lane == layer.lane)
     val dp = host[DispatchPlugin]
     val ram = host.get[CsrRamService]
     val sp = host[ReschedulePlugin]
@@ -77,7 +77,7 @@ class CsrAccessPlugin(val layer : LaneLayer,
       op.addRsSpec(RS1, injectAt)
     }
 
-    val age = layer.el.getExecuteAge(injectAt)
+    val age = layer.lane.getExecuteAge(injectAt)
     val flushPort = sp.newFlushPort(age, laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
     val trapPort = ts.newTrap(age, Execute.LANE_AGE_WIDTH)
 

src/main/scala/vexiiriscv/execute/ExecutionUnitElementSimple.scala

@@ -71,9 +71,9 @@ abstract class ExecutionUnitElementSimple(layer : LaneLayer) extends FiberPlugin
   val SEL = Payload(Bool())
 
   class Logic extends ExecuteUnitElementSimple.Api(layer,  host.find[SrcPlugin](_.layer == layer), SEL, rsUnsignedPlugin = host.get[RsUnsignedPlugin].getOrElse(null)) with Area with PostInitCallback {
-    val el = layer.el
+    val el = layer.lane
     val srcp = srcPlugin
-    val ifp = host.find[IntFormatPlugin](_.lane == layer.el)
+    val ifp = host.find[IntFormatPlugin](_.lane == layer.lane)
     val uopRetainer = retains(el.uopLock, srcp.elaborationLock, ifp.elaborationLock)
     val euPipelineRetainer = retains(el.pipelineLock)
 

src/main/scala/vexiiriscv/execute/Service.scala

@@ -23,21 +23,21 @@ case class RsSpec(rs : RfRead){
   var from = 0
 }
 
-class LaneLayer(val name : String, val el : ExecuteLaneService, var priority : Int){
+class LaneLayer(val name : String, val lane : ExecuteLaneService, var priority : Int){
   val uops = mutable.LinkedHashMap[MicroOp, UopLayerSpec]()
-  el.add(this)
+  lane.add(this)
 
   def apply(uop: MicroOp) = uops(uop)
-  def add(uop: MicroOp) = uops.getOrElseUpdate(uop, new UopLayerSpec(uop, this, el))
-  def laneName = el.laneName
+  def add(uop: MicroOp) = uops.getOrElseUpdate(uop, new UopLayerSpec(uop, this, lane))
+  def laneName = lane.laneName
   def getRsUseAtMin(): Int = {
     uops.flatMap(_._2.rs.map(_._2.from)).fold(100)(_ min _)
   }
 
   def doChecks(): Unit = {
     for(uop <- uops.values) uop.doCheck()
   }
-  class Execute(id: Int) extends CtrlLaneMirror(el.execute(id))
+  class Execute(id: Int) extends CtrlLaneMirror(lane.execute(id))
 }
 
 class UopLayerSpec(val uop: MicroOp, val elImpl : LaneLayer, val el : ExecuteLaneService) {

src/main/scala/vexiiriscv/execute/SimdAddRawPlugin.scala

@@ -21,9 +21,9 @@ object SimdAddRaw{
 class SimdAddRawPlugin(val layer : LaneLayer) extends FiberPlugin  {
   import SimdAddRaw._
   val logic = during setup new Area {
-    val wbp = host.find[WriteBackPlugin](p => p.rf == IntRegFile && p.lane == layer.el)
-    val earlyLock = retains(layer.el.uopLock, wbp.elaborationLock)
-    val lateLock = retains(layer.el.pipelineLock)
+    val wbp = host.find[WriteBackPlugin](p => p.rf == IntRegFile && p.lane == layer.lane)
+    val earlyLock = retains(layer.lane.uopLock, wbp.elaborationLock)
+    val lateLock = retains(layer.lane.pipelineLock)
     awaitBuild()
 
     val add4 = layer.add(ADD4)
@@ -39,16 +39,16 @@ class SimdAddRawPlugin(val layer : LaneLayer) extends FiberPlugin  {
     wbp.addMicroOp(wb, add4)
 
     val SEL = Payload(Bool())
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     add4.addDecoding(SEL -> True)
 
     earlyLock.release()
 
     //Let's define some logic in the execute lane [0]
     val process = new layer.Execute(id = 0) {
       //Get the RISC-V RS1/RS2 values from the register file
-      val rs1 = layer.el(IntRegFile, RS1).asUInt
-      val rs2 = layer.el(IntRegFile, RS2).asUInt
+      val rs1 = layer.lane(IntRegFile, RS1).asUInt
+      val rs2 = layer.lane(IntRegFile, RS2).asUInt
 
       //Do some computation
       val rd = UInt(32 bits)

src/main/scala/vexiiriscv/execute/fpu/FpuAddPlugin.scala

@@ -21,13 +21,13 @@ class FpuAddPlugin(val layer : LaneLayer,
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
     val fasp = host[FpuAddSharedPlugin]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fasp.elaborationLock, fup.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fasp.elaborationLock, fup.elaborationLock)
     awaitBuild()
 
     val addPort = fasp.createPort(List(addAt), FpuUtils.unpackedConfig, FpuUtils.unpackedConfig)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)

src/main/scala/vexiiriscv/execute/fpu/FpuClassPlugin.scala

@@ -17,14 +17,14 @@ class FpuClassPlugin(val layer : LaneLayer, var wbAt : Int = 0) extends FiberPlu
 
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, iwbp.elaborationLock)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, iwbp.elaborationLock)
     awaitBuild()
 
     val iwb = iwbp.access(wbAt)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)

src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala

@@ -31,19 +31,19 @@ class FpuCmpPlugin(val layer : LaneLayer,
 
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
-    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.el && p.rf == FloatRegFile)
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fwbp.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
+    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.lane && p.rf == FloatRegFile)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fwbp.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
     awaitBuild()
 
     val ffwb = ffwbp.createPort(List(cmpAt))
     val fwb = fwbp.createPort(floatWbAt)
     val iwb = iwbp.access(intWbAt)
 
-    layer.el.setDecodingDefault(SEL_FLOAT, False)
-    layer.el.setDecodingDefault(SEL_CMP, False)
+    layer.lane.setDecodingDefault(SEL_FLOAT, False)
+    layer.lane.setDecodingDefault(SEL_CMP, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -132,7 +132,7 @@ class FpuCmpPlugin(val layer : LaneLayer,
 
     val onFloatWb = new layer.Execute(floatWbAt) {
       fwb.valid := SEL_FLOAT
-      fwb.payload := (FLOAT_OP === FpuCmpFloatOp.MIN_MAX && onCmp.MIN_MAX_RS2).mux(up(layer.el(FloatRegFile, RS2)), up(layer.el(FloatRegFile, RS1)))
+      fwb.payload := (FLOAT_OP === FpuCmpFloatOp.MIN_MAX && onCmp.MIN_MAX_RS2).mux(up(layer.lane(FloatRegFile, RS2)), up(layer.lane(FloatRegFile, RS1)))
       val doNan = RS1_FP.isNan && RS2_FP.isNan && FLOAT_OP === FpuCmpFloatOp.MIN_MAX
       val wb = fwb.payload
       when(doNan) {

src/main/scala/vexiiriscv/execute/fpu/FpuDivPlugin.scala

@@ -20,8 +20,8 @@ class FpuDivPlugin(val layer : LaneLayer,
     val fup = host[FpuUnpackerPlugin]
     val fpp = host[FpuPackerPlugin]
     val dr  = host[DivReuse]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -31,7 +31,7 @@ class FpuDivPlugin(val layer : LaneLayer,
     )
     val packPort = fpp.createPort(List(exeAt), packParam)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)

src/main/scala/vexiiriscv/execute/fpu/FpuF2iPlugin.scala

@@ -26,16 +26,16 @@ class FpuF2iPlugin(val layer : LaneLayer,
 
   val logic = during setup new Area{
     val fup = host[FpuUnpackerPlugin]
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val ffwbp = host.find[FpuFlagsWritebackPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, iwbp.elaborationLock, ffwbp.elaborationLock)
     awaitBuild()
 
     val ffwb = ffwbp.createPort(List(intWbAt))
     val iwb = iwbp.access(intWbAt)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def f2i(uop: MicroOp, size : Int, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -105,9 +105,9 @@ class FpuF2iPlugin(val layer : LaneLayer,
       val round = low.msb ## low.dropHigh(1).orR
 
       val halfRater = halfRate generate new Area {
-        val firstCycle = RegNext(!layer.el.isFreezed()) init (True)
+        val firstCycle = RegNext(!layer.lane.isFreezed()) init (True)
         val freezeIt = isValid && SEL && firstCycle
-        layer.el.freezeWhen(freezeIt)
+        layer.lane.freezeWhen(freezeIt)
       }
 
       val inverter = Delay(Mux(onShift.resign, ~unsigned, unsigned) + onShift.incrementPatched, halfRate.toInt)

src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala

@@ -29,8 +29,8 @@ class FpuMulPlugin(val layer : LaneLayer,
     val fpp = host[FpuPackerPlugin]
     val fasp = host[FpuAddSharedPlugin]
     val mp  = host[MulReuse]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -49,7 +49,7 @@ class FpuMulPlugin(val layer : LaneLayer,
     val addPort = withFma generate fasp.createPort(List(packAt), addParam, FpuUtils.unpackedConfig)
 
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
@@ -134,7 +134,7 @@ class FpuMulPlugin(val layer : LaneLayer,
     }
     import norm._
 
-    val onPack = new layer.el.Execute(packAt) {
+    val onPack = new layer.lane.Execute(packAt) {
       val nv = False
 
       val mode = FloatMode.NORMAL()

src/main/scala/vexiiriscv/execute/fpu/FpuMvPlugin.scala

@@ -20,17 +20,17 @@ class FpuMvPlugin(val layer : LaneLayer,
   val SEL_INT = Payload(Bool())
 
   val logic = during setup new Area{
-    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.el && p.rf == FloatRegFile)
-    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.el)
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fwbp.elaborationLock, iwbp.elaborationLock)
+    val fwbp = host.find[WriteBackPlugin](p => p.lane == layer.lane && p.rf == FloatRegFile)
+    val iwbp = host.find[IntFormatPlugin](p => p.lane == layer.lane)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fwbp.elaborationLock, iwbp.elaborationLock)
     awaitBuild()
 
     val fwb = fwbp.createPort(floatWbAt)
     val iwb = iwbp.access(intWbAt)
 
-    layer.el.setDecodingDefault(SEL_FLOAT, False)
-    layer.el.setDecodingDefault(SEL_INT, False)
+    layer.lane.setDecodingDefault(SEL_FLOAT, False)
+    layer.lane.setDecodingDefault(SEL_INT, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(decodings)
@@ -63,14 +63,14 @@ class FpuMvPlugin(val layer : LaneLayer,
 
     val onIntWb = new layer.Execute(intWbAt) {
       iwb.valid   := SEL_INT
-      iwb.payload := up(layer.el(FloatRegFile, RS1)).resized
+      iwb.payload := up(layer.lane(FloatRegFile, RS1)).resized
     }
 
     val onFloatWb = new layer.Execute(floatWbAt) {
       fwb.valid := SEL_FLOAT
-      fwb.payload(31 downto 0) := up(layer.el(IntRegFile, RS1))(31 downto 0)
+      fwb.payload(31 downto 0) := up(layer.lane(IntRegFile, RS1))(31 downto 0)
       if(Riscv.RVD.get) {
-        fwb.payload(63 downto 32) := muxDouble(FORMAT)(up(layer.el(IntRegFile, RS1))(63 downto 32))(B"xFFFFFFFF")
+        fwb.payload(63 downto 32) := muxDouble(FORMAT)(up(layer.lane(IntRegFile, RS1))(63 downto 32))(B"xFFFFFFFF")
       }
     }
 

src/main/scala/vexiiriscv/execute/fpu/FpuSqrtPlugin.scala

@@ -21,8 +21,8 @@ class FpuSqrtPlugin(val layer : LaneLayer,
     val fup = host[FpuUnpackerPlugin]
     val fpp = host[FpuPackerPlugin]
     val mp  = host[MulReuse]
-    val buildBefore = retains(layer.el.pipelineLock)
-    val uopLock = retains(layer.el.uopLock, fup.elaborationLock, fpp.elaborationLock)
+    val buildBefore = retains(layer.lane.pipelineLock)
+    val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock)
     awaitBuild()
 
     val packParam = FloatUnpackedParam(
@@ -32,7 +32,7 @@ class FpuSqrtPlugin(val layer : LaneLayer,
     )
     val packPort = fpp.createPort(List(exeAt), packParam)
 
-    layer.el.setDecodingDefault(SEL, False)
+    layer.lane.setDecodingDefault(SEL, False)
     def add(uop: MicroOp, decodings: (Payload[_ <: BaseType], Any)*) = {
       val spec = layer.add(uop)
       spec.addDecoding(SEL -> True)
@@ -68,7 +68,7 @@ class FpuSqrtPlugin(val layer : LaneLayer,
 
       val unscheduleRequest = RegNext(isCancel) clearWhen (isReady) init (False)
       val freeze = isValid && SEL && !sqrt.io.output.valid & !unscheduleRequest
-      layer.el.freezeWhen(freeze)
+      layer.lane.freezeWhen(freeze)
 
       val exp = (RS1_FP.exponent >>| 1)
       val scrap = sqrt.io.output.remain =/= 0