Merge branch 'fpu_internal' into dev

README.md

@@ -14,6 +14,8 @@ VexiiRiscv (Vex2Risc5) is the successor of VexRiscv. Work in progress, here are
 - Pipeline visualisation in simulation via Konata
 - Lock step simulation via RVLS and Spike
 
+Overall the goal is to have a design which can stretch (through configuration) from Cortex M0 up to a Cortex A53 and potentialy beyond.
+
 Here is the online documentation : 
 
 - https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Introduction/#

src/main/scala/spinal/lib/misc/AstWalker.scala

@@ -0,0 +1,87 @@
+//package spinal.lib.misc
+//
+//import spinal.core._
+//import spinal.core.internals.{BaseNode, Expression}
+//
+//import scala.collection.mutable
+//import scala.collection.mutable.ArrayBuffer
+//
+//class AstWalker {
+//  def apply(from: BaseNode)(body : (BaseNode, Int) => Boolean): Unit = {
+//    val walkedId = GlobalData.get.allocateAlgoIncrementale()
+//
+//    rec(from)
+//    def rec(driver : BaseNode) : Unit = {
+//      foreach(from) { (node, latency) =>
+//        if (body(node, latency)) {
+//          rec(driver)
+//        }
+//      }
+//    }
+//
+//    def foreach(that: BaseNode)(onUp : (BaseNode, Int) => Unit): Unit = {
+//      if(that.algoIncrementale == walkedId)
+//        return
+//      that.algoIncrementale = walkedId
+//      if(that == from)
+//        return
+//
+//      that match{
+//        case that : Mem[_] => {
+//          that.foreachStatements{
+//            case port : MemWrite =>
+//              port.foreachDrivingExpression(input => {
+//                onUp(input, 1)
+//              })
+//            case port : MemReadWrite =>
+//              port.foreachDrivingExpression(input => {
+//                onUp(input, 1)
+//              })
+//            case port : MemReadSync =>
+//            case port : MemReadAsync =>
+//            //TODO other ports
+//          }
+//        }
+//        case that : BaseType => { //TODO IR when conds
+//          def foreachInputs(func : (BaseNode) => Unit) = {
+//            that.foreachStatements(s => {
+//              s.foreachDrivingExpression(input => {
+//                func(input)
+//              })
+//              s.walkParentTreeStatementsUntilRootScope(tree => tree.foreachDrivingExpression(input => {
+//                func(input)
+//              }))
+//            })
+//          }
+//          if(that.isReg){
+//            foreachInputs(input => onUp(input, 1))
+//          } else {
+//            foreachInputs(input => {
+//              onUp(input, 0)
+//            })
+//          }
+//        }
+//        case that : MemReadSync =>
+//          that.foreachDrivingExpression(input => onUp(input, 1))
+//          onUp(that.mem, 1)
+//        case that : MemReadWrite =>
+//          that.foreachDrivingExpression{input =>
+//            val lat = if(input == that.data || input == that.mask) 2 else 1
+//            onUp(input, 1)
+//          }
+//          onUp(that.mem, 1)
+//        case that : MemReadAsync =>
+//          that.foreachDrivingExpression(input => {
+//            onUp(input, 0)
+//          })
+//          onUp(that.mem,0)
+//        case that : Expression => {
+//          that.foreachDrivingExpression(input => {
+//            onUp(input, 0)
+//          })
+//        }
+//      }
+//    }
+//
+//  }
+//}

src/main/scala/spinal/lib/misc/pipeline/NodeLaneApi.scala

@@ -0,0 +1,55 @@
+package spinal.lib.misc.pipeline
+
+import spinal.core._
+
+trait NodeLaneApi{
+  def nodeLink: Node
+  def laneName: String
+  def LANE_SEL: Payload[Bool] = CtrlLaneApi.LANE_SEL
+
+  private val _c = nodeLink
+
+  def isValid: Bool = _c.isValid
+  def isReady : Bool = _c.isReady
+  def isCancel : Bool = _c.isCancel
+
+  def apply[T <: Data](that: Payload[T]): T = _c.apply(that, laneName)
+  def apply[T <: Data](that: Payload[T], subKey : Any): T = _c.apply(that, laneName + "_" + subKey.toString)
+  def insert[T <: Data](that: T): Payload[T] = {
+    val p = Payload(that)
+    apply(p) := that
+    p
+  }
+
+
+  abstract class NodeMirror(node : Node) extends NodeBaseApi {
+    override def valid = node(LANE_SEL, laneName)
+    override def ready = node.ready
+    override def cancel = node.cancel
+    override def isValid: Bool = node(LANE_SEL, laneName)
+    override def isReady: Bool = node.isReady
+    override def isFiring = valid && isReady && !isCancel
+    override def isMoving = valid && (isReady || isCancel)
+//    override def isCancel: Bool = node.isCancel
+    override def isCanceling = valid && isCancel
+    override def apply(key: NamedTypeKey) = ???
+    override def apply[T <: Data](key: Payload[T]) = node(key, laneName)
+    override def apply(subKey: Seq[Any]) = ???
+    def transactionSpawn = valid && !RegNext(valid, False).clearWhen(isReady || isCancel)
+  }
+
+
+  implicit def stageablePiped2[T <: Data](stageable: Payload[T]): T = this (stageable)
+  implicit def bundlePimper[T <: Bundle](stageable: Payload[T]): BundlePimper[T] = new BundlePimper[T](this (stageable))
+  class BundlePimper[T <: Bundle](pimped: T) {
+    def :=(that: T): Unit = pimped := that
+  }
+
+  class Area(from : NodeLaneApi = this) extends NodeLaneMirror(from)
+}
+
+class NodeLaneMirror(from : NodeLaneApi) extends spinal.core.Area with NodeLaneApi {
+  override def nodeLink: Node = from.nodeLink
+  override def laneName: String = from.laneName
+  override def LANE_SEL: Payload[Bool] = from.LANE_SEL
+}

src/main/scala/spinal/lib/misc/test/MultithreadedFunSuite.scala

@@ -13,7 +13,7 @@ object HeavyLock
 
 class MultithreadedFunSuite(threadCount : Int) extends AnyFunSuite {
   val finalThreadCount = if(threadCount > 0) threadCount else {
-    new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount
+    new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount*4
   }
   implicit val ec = ExecutionContext.fromExecutorService(
     new ForkJoinPool(finalThreadCount, ForkJoinPool.defaultForkJoinWorkerThreadFactory, null, true)

src/main/scala/vexiiriscv/Global.scala

@@ -35,6 +35,7 @@ object Global extends AreaRoot{
   val TVAL = Payload(Bits(TVAL_WIDTH bits))
   val TRAP = Payload(Bool())
   val COMMIT = Payload(Bool())
+  val COMPLETED = Payload(Bool())
 
   def HART_ID_WIDTH = log2Up(HART_COUNT)
   val HART_ID = Payload(UInt(HART_ID_WIDTH bits))