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Submodule NaxSoftware
updated
6 files
+12 −0 | baremetal/hpm/makefile | |
+57 −0 | baremetal/hpm/src/main.c | |
+307 −1 | baremetal/vexiiriscv/src/crt.S | |
+9 −0 | buildroot/README.md | |
+1 −1 | debian_litex/README.md | |
+386 −130 | debian_litex/linux/.config |
Submodule SpinalHDL
updated
87 files
Submodule riscv-isa-sim
updated
3 files
+5 −0 | riscv/processor.cc | |
+1 −1 | softfloat/softfloat.h | |
+1 −1 | softfloat/softfloat_state.c |
Submodule rvls
updated
10 files
+3 −1 | bindings/jni/rvls/jni/Frontend.java | |
+21 −7 | bindings/spinal/rvls/spinal/Tracer.scala | |
+19 −2 | src/ascii_frontend.cpp | |
+50 −23 | src/coherency.cpp | |
+11 −1 | src/coherency.hpp | |
+5 −0 | src/context.cpp | |
+1 −0 | src/context.hpp | |
+22 −5 | src/hart.cpp | |
+4 −0 | src/hart.hpp | |
+18 −2 | src/jni_frontend.cpp |
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//package spinal.lib.misc | ||
// | ||
//import spinal.core._ | ||
//import spinal.core.internals.{BaseNode, Expression} | ||
// | ||
//import scala.collection.mutable | ||
//import scala.collection.mutable.ArrayBuffer | ||
// | ||
//class AstWalker { | ||
// def apply(from: BaseNode)(body : (BaseNode, Int) => Boolean): Unit = { | ||
// val walkedId = GlobalData.get.allocateAlgoIncrementale() | ||
// | ||
// rec(from) | ||
// def rec(driver : BaseNode) : Unit = { | ||
// foreach(from) { (node, latency) => | ||
// if (body(node, latency)) { | ||
// rec(driver) | ||
// } | ||
// } | ||
// } | ||
// | ||
// def foreach(that: BaseNode)(onUp : (BaseNode, Int) => Unit): Unit = { | ||
// if(that.algoIncrementale == walkedId) | ||
// return | ||
// that.algoIncrementale = walkedId | ||
// if(that == from) | ||
// return | ||
// | ||
// that match{ | ||
// case that : Mem[_] => { | ||
// that.foreachStatements{ | ||
// case port : MemWrite => | ||
// port.foreachDrivingExpression(input => { | ||
// onUp(input, 1) | ||
// }) | ||
// case port : MemReadWrite => | ||
// port.foreachDrivingExpression(input => { | ||
// onUp(input, 1) | ||
// }) | ||
// case port : MemReadSync => | ||
// case port : MemReadAsync => | ||
// //TODO other ports | ||
// } | ||
// } | ||
// case that : BaseType => { //TODO IR when conds | ||
// def foreachInputs(func : (BaseNode) => Unit) = { | ||
// that.foreachStatements(s => { | ||
// s.foreachDrivingExpression(input => { | ||
// func(input) | ||
// }) | ||
// s.walkParentTreeStatementsUntilRootScope(tree => tree.foreachDrivingExpression(input => { | ||
// func(input) | ||
// })) | ||
// }) | ||
// } | ||
// if(that.isReg){ | ||
// foreachInputs(input => onUp(input, 1)) | ||
// } else { | ||
// foreachInputs(input => { | ||
// onUp(input, 0) | ||
// }) | ||
// } | ||
// } | ||
// case that : MemReadSync => | ||
// that.foreachDrivingExpression(input => onUp(input, 1)) | ||
// onUp(that.mem, 1) | ||
// case that : MemReadWrite => | ||
// that.foreachDrivingExpression{input => | ||
// val lat = if(input == that.data || input == that.mask) 2 else 1 | ||
// onUp(input, 1) | ||
// } | ||
// onUp(that.mem, 1) | ||
// case that : MemReadAsync => | ||
// that.foreachDrivingExpression(input => { | ||
// onUp(input, 0) | ||
// }) | ||
// onUp(that.mem,0) | ||
// case that : Expression => { | ||
// that.foreachDrivingExpression(input => { | ||
// onUp(input, 0) | ||
// }) | ||
// } | ||
// } | ||
// } | ||
// | ||
// } | ||
//} |
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package spinal.lib.misc.pipeline | ||
|
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import spinal.core._ | ||
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trait NodeLaneApi{ | ||
def nodeLink: Node | ||
def laneName: String | ||
def LANE_SEL: Payload[Bool] = CtrlLaneApi.LANE_SEL | ||
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private val _c = nodeLink | ||
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def isValid: Bool = _c.isValid | ||
def isReady : Bool = _c.isReady | ||
def isCancel : Bool = _c.isCancel | ||
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def apply[T <: Data](that: Payload[T]): T = _c.apply(that, laneName) | ||
def apply[T <: Data](that: Payload[T], subKey : Any): T = _c.apply(that, laneName + "_" + subKey.toString) | ||
def insert[T <: Data](that: T): Payload[T] = { | ||
val p = Payload(that) | ||
apply(p) := that | ||
p | ||
} | ||
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abstract class NodeMirror(node : Node) extends NodeBaseApi { | ||
override def valid = node(LANE_SEL, laneName) | ||
override def ready = node.ready | ||
override def cancel = node.cancel | ||
override def isValid: Bool = node(LANE_SEL, laneName) | ||
override def isReady: Bool = node.isReady | ||
override def isFiring = valid && isReady && !isCancel | ||
override def isMoving = valid && (isReady || isCancel) | ||
// override def isCancel: Bool = node.isCancel | ||
override def isCanceling = valid && isCancel | ||
override def apply(key: NamedTypeKey) = ??? | ||
override def apply[T <: Data](key: Payload[T]) = node(key, laneName) | ||
override def apply(subKey: Seq[Any]) = ??? | ||
def transactionSpawn = valid && !RegNext(valid, False).clearWhen(isReady || isCancel) | ||
} | ||
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implicit def stageablePiped2[T <: Data](stageable: Payload[T]): T = this (stageable) | ||
implicit def bundlePimper[T <: Bundle](stageable: Payload[T]): BundlePimper[T] = new BundlePimper[T](this (stageable)) | ||
class BundlePimper[T <: Bundle](pimped: T) { | ||
def :=(that: T): Unit = pimped := that | ||
} | ||
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class Area(from : NodeLaneApi = this) extends NodeLaneMirror(from) | ||
} | ||
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class NodeLaneMirror(from : NodeLaneApi) extends spinal.core.Area with NodeLaneApi { | ||
override def nodeLink: Node = from.nodeLink | ||
override def laneName: String = from.laneName | ||
override def LANE_SEL: Payload[Bool] = from.LANE_SEL | ||
} |
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