HDL support for VS Code
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Updated
Jul 30, 2024 - TypeScript
HDL support for VS Code
Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.
This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.
An abstraction library for interfacing EDA tools
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Practice Codes of Verilog Language
A generic verification interface to Icarus Verilog using TCP sockets
📦 Prebuilt Icarus Verilog simulator package for x64 Linux.
All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL
RTL implementation of a MoldUPD64 receiver.
Guides on how to install a SystemVerilog toolchain on different operating systems
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