1.3.0

• Added new option for supporting RVfpga-ViDBo and RVfpga-Pipeline (pull #12)
• Fixed "program_fpga" target errors (issue #11)

1.2.0

• Added compatibility with PIO Core 6.0
• Improved support for a bare assembly programming

1.1.0

• Updated the OpenOCD package to v0.11
• Updated default FPGA bitstream
• Updated default upload command

1.0.3

• Updated version requirement for the Whisper package

1.0.2

• Allow specifying custom binary name for the Verilator tool

1.0.1

• Changed the default env name in examples to rvfpga
• Allowed overriding a previously generated trace file from Verilator (issue #3)

1.0.0

• Added support for Whisper ISS tool
• Updated WD RISC-V Firmware Package
• Allowed using PSP without RTOS feature
• Minor bugfixes and improvements

0.1.2

• Minor bugfixes

0.1.1

• Minor bugfixes

0.1.0

• New board Digilent Nexys A7
• Support for WD Firmware
• Documentation for platform configuration