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This repo provide an index of VLSI content creators and their materials

140 18 Updated Aug 21, 2024

RTL to GDS via Cadence Tools

6 4 Updated May 17, 2022

EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

Jupyter Notebook 144 27 Updated Nov 27, 2024

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…

Verilog 15 3 Updated Apr 29, 2024

Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023

Verilog 14 1 Updated Aug 10, 2023

Static Timing Analysis Full Course

46 12 Updated Jan 14, 2023

Final Project for NTHU Advanced Logic Synthesis

C++ 2 Updated Dec 13, 2021

Coursework of NTHU CS613200 Advanced Logic Synthesis

C++ 6 Updated Jun 22, 2023

2021 NTHU CS6132 (CS613200) Advanced Logic Synthesis Course Project (include Technology Mapping)

C++ 7 Updated Dec 14, 2023

Physical Design for Nanometer ICs (Spring, 2017)

C++ 2 1 Updated Jul 4, 2019

Multimedia SoC design (2020 Fall)

C 4 Updated Jan 21, 2021

Physical Design (2020 Spring)

C++ 3 Updated Jun 17, 2020

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

Tcl 17 4 Updated Dec 30, 2022

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical i…

HTML 219 55 Updated Jul 26, 2024

Routing Visualization for Physical Design

Python 18 4 Updated Dec 24, 2018

Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)

C++ 39 17 Updated Dec 24, 2018

all material for the VSD-HDP program

Verilog 1 Updated Dec 17, 2023

Curriculum for a university course to teach chip design using open source EDA tools

Jupyter Notebook 57 11 Updated Oct 21, 2023

List of awesome open source hardware tools, generators, and reusable designs

Python 1,957 182 Updated Nov 21, 2024
Verilog 9 5 Updated May 30, 2022

100 Days of RTL

SystemVerilog 345 102 Updated Aug 15, 2024
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