soc: add OpenHW Group CVA6 SoC #77732

WorldofJARcraft · 2024-08-29T09:29:18Z

Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available.
This commit adds support for the 64-bit configuration of CVA6, as well as two slightly different SoCs (the main difference being the Ethernet subsystem).
The configuration can also optionally target the hardware simulation environment (test harness) of the CVA6 project and can indicate test/failure to the environment.

WorldofJARcraft · 2024-09-02T12:54:37Z

Full support for this SoC depends on drivers for the Ethernet subsystem: #73986, #73982, #73926

nordicjm · 2024-11-06T11:53:18Z

boards/openhwgroup/cv32a6_arty_a7_100/Kconfig.cv32a6_arty_a7_100

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV32A6_ARTY_A7_100


split this into commits, not going to review 77 files spanning multiple boards, multiple socs and even samples in a single commits

I have removed the boards and samples from this PR and created new PRs:

boards: openhwgroup: add CV64A6 on GenesysII board #81019

boards: openhwgroup: add CVA6 on GenesysII board #81015

boards: openhwgroup: add CVA6 on Arty A7 board #81018

boards: openhwgroup: add CVA6 Testbench #81017
I have kept the 32-bit and the 64-bit variants of the same board in the same PR, as they are otherwise identical.

Have this PR have a soc (in one commit), drivers (each in different commits) and one board (in another commit), then once that is merged you can add additional boards in a new PR each with their own commit

The Ethernet subsystem is not specific to this hardware (e.g., it is also used on ARM boards), so I will leave it as separate PRs.
This PR now has one commit with the SoC and one with a board in 32 and 64 bit variants.

kartben · 2024-11-06T12:00:44Z

@WorldofJARcraft please don't forget that new boards must come with associated documentation. See https://docs.zephyrproject.org/latest/hardware/porting/board_porting.html#contributing-your-board

WorldofJARcraft · 2024-11-06T12:04:30Z

@WorldofJARcraft please don't forget that new boards must come with associated documentation. See https://docs.zephyrproject.org/latest/hardware/porting/board_porting.html#contributing-your-board

Thank you for the reminder, I will finalize my changes and add the documentation before un-drafting the PR.

nordicjm

apply comments throughout, they have only been added to the first instance

nordicjm · 2024-11-07T10:30:08Z

dts/riscv/openhwgroup/cv32a6.dtsi

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: Apache-2.0


/* comment style

nordicjm · 2024-11-07T10:30:22Z

dts/riscv/openhwgroup/cv32a6.dtsi

+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32ima";
+


Suggested change

nordicjm · 2024-11-07T10:30:38Z

dts/riscv/openhwgroup/cv32a6.dtsi

+			};
+		};
+	};
+


Suggested change

dts/riscv/openhwgroup/cva6.dtsi

nordicjm · 2024-11-07T10:31:06Z

dts/riscv/openhwgroup/cva6.dtsi

+	ranges;
+
+	memory0:memory@80000000 {
+	    device_type = "memory";


tab indents

nordicjm · 2024-11-07T10:34:55Z

soc/openhwgroup/cva6/cv32a6/Kconfig.soc

+	default "cv32a6" if SOC_SERIES_CV32A6
+
+config SOC
+	default "cv32a6" if SOC_CV32A6


do you really need a soc series and a soc if they are the same value? If not, remove the soc series from Kconfig and soc.yml and just have the soc

There are several slightly different versions of the CVA6 32-bit SOC: with and without MMU, with and without FPU, and a RV32E version is currently being developed. I have added the least common denominator here, future PRs can add the other variants as soon as they are finalized.

All of the RV32I SoCs work with the config I provided, but the RV32E really needs to be separate (it has fewer registers).

nordicjm · 2024-11-07T10:36:23Z

soc/openhwgroup/cva6/cv64a6/Kconfig

+# SPDX-License-Identifier: Apache-2.0
+# RISCV64 OpenHW Group cva6 configuration options
+
+config SOC_CV64A6_IMAFDC


have a config SOC_CV64A6 symbol which selects common this, then you can select the unique ones in the separate Kconfigs. And select the common Kconfig from Kconfig.soc

nordicjm · 2024-11-07T10:36:43Z

soc/openhwgroup/cva6/cv64a6/Kconfig.soc

+	default "cv64a6" if SOC_CV64A6_IMAFDC
+	default "cv64a6" if SOC_CV64A6_IMAC


Suggested change

default "cv64a6" if SOC_CV64A6_IMAFDC

default "cv64a6" if SOC_CV64A6_IMAC

default "cv64a6" if SOC_CV64A6

nordicjm · 2024-11-07T10:36:53Z

soc/openhwgroup/cva6/cva6.h

+
+#include <stdint.h>
+
+void z_cva6_finish_test(const int32_t status);


what is this?

One of the "board" configurations from the other PRs describes a verification harness in which the CVA6 CPU is run in verilator (a HDL simulator). This is used to run test programs in the simulator and check whether the CPU behaves as expected. To this end, the simulator provides an interface that allows completing the test case successfully or with an error code. This is exposed via this SoC-specific function.
The samples I added in #81017 show how this can be used in software.

I have added a comment that explains what the function does.

Should I remove this functionality from this PR and re-introduce it with the board that actually uses this?

nordicjm · 2024-11-07T10:37:55Z

dts/riscv/openhwgroup/cv32a6.dtsi

+
+#include "cva6.dtsi"
+
+// minimal configuration of CVA6 32-bit CPUs: no instruction set extensions,


Capitalise first letter of comments i.e. English

WorldofJARcraft · 2024-11-07T15:16:04Z

I have incorporated the requested changes and re-written the commits.

WorldofJARcraft · 2024-11-08T11:38:22Z

Documentation for the new boards in this PR has been added.

WorldofJARcraft · 2024-11-08T14:13:51Z

The support/ariane.cfg file (openocd configuration) is shared between the 32- and the 64-bit version of the board I am adding. Is there a good place to move it, such that there is only one copy?

boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts

boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig

boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig

dts/riscv/openhwgroup/cv32a6.dtsi

dts/riscv/openhwgroup/cv64a6.dtsi

soc/openhwgroup/cva6/cv64a6/Kconfig

fkokosinski · 2024-11-12T11:30:43Z

soc/openhwgroup/cva6/cva6.h

+/*
+ *
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX - License - Identifier : Apache-2.0


Suggested change

* SPDX - License - Identifier : Apache-2.0

* SPDX-License-Identifier: Apache-2.0

soc/openhwgroup/cva6/soc.yml

fkokosinski · 2024-11-12T11:32:11Z

soc/openhwgroup/cva6/soc_cache_management.c

+void arch_dcache_enable(void)
+{
+	__asm__ volatile("csrwi 0x7C1, 0x01");
+}
+
+void arch_dcache_disable(void)
+{
+	__asm__ volatile("csrwi 0x7C1, 0x00");
+}


A comment or two would be nice to explain what we're doing here, i.e. what is the 0x7c1 CSR, what are those bits that we're writing/clearing and so on.

Added a comment

Thanks for the comment. Let's use here the csr_write() macro from include/zephyr/arch/riscv/csr.h

Done. I have also created defines for the CSR numbers and enable/disable values and moved them to the cva6.h header.

fkokosinski · 2024-11-12T11:34:23Z

soc/openhwgroup/cva6/soc_poweroff_fpga.c

+	for (;;) {
+	}


Doesn't seem to look like a poweroff, could be misleading for the user.

I will remove this file from the PR.
I have only added it such that my samples for the testbench board compile on the other CVA6 boards as well. I think a better solution is to simply depend on the "proper" power off at configuration time for the samples.

Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 64-bit and a 64-bit configuration of CVA6, respectively. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

WorldofJARcraft marked this pull request as draft August 29, 2024 09:29

WorldofJARcraft force-pushed the openhwgroup-cv64a6-soc branch 3 times, most recently from f442e4e to eda4bed Compare August 29, 2024 13:35

WorldofJARcraft mentioned this pull request Aug 29, 2024

boards: openhwgroup: add CV64A6 on GenesysII board #77734

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WorldofJARcraft mentioned this pull request Oct 8, 2024

drivers: dma: Add Xilinx AXI DMA driver #73926

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This was referenced Nov 6, 2024

boards: openhwgroup: add CV64A6 Testbench #77789

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boards: openhwgroup: add CV64A6 on GenesysII board #77792

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Blueballs #80772

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		default "cv64a6" if SOC_CV64A6_IMAFDC
		default "cv64a6" if SOC_CV64A6_IMAC

	default "cv64a6" if SOC_CV64A6_IMAFDC
	default "cv64a6" if SOC_CV64A6_IMAC
	default "cv64a6" if SOC_CV64A6


		#include <stdint.h>

		void z_cva6_finish_test(const int32_t status);


		#include "cva6.dtsi"

		// minimal configuration of CVA6 32-bit CPUs: no instruction set extensions,

	* SPDX - License - Identifier : Apache-2.0
	* SPDX-License-Identifier: Apache-2.0

soc: add OpenHW Group CVA6 SoC #77732

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soc: add OpenHW Group CVA6 SoC #77732

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WorldofJARcraft commented Aug 29, 2024

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kartben commented Nov 6, 2024 • edited Loading

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WorldofJARcraft commented Nov 7, 2024

WorldofJARcraft commented Nov 8, 2024

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kartben commented Nov 6, 2024 •

edited

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