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Henk-Jan Lebbink edited this page Aug 22, 2017 · 14 revisions

SWAPGS — Swap GS Base Register

Opcode Instruction Op/ En 64-Bit Mode Compat/ Leg Mode Description
0F 01 F8 SWAPGS ZO Valid Invalid Exchanges the current GS base register value with the value contained in MSR address C0000102H.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
ZO NA NA NA NA

Description

SWAPGS exchanges the current GS base register value with the value contained in MSR address C0000102H (IA32_KERNEL_GS_BASE). The SWAPGS instruction is a privileged instruction intended for use by system soft- ware.

When using SYSCALL to implement system calls, there is no kernel stack at the OS entry point. Neither is there a straightforward method to obtain a pointer to kernel structures from which the kernel stack pointer could be read. Thus, the kernel cannot save general purpose registers or reference memory.

By design, SWAPGS does not require any general purpose registers or memory operands. No registers need to be saved before using the instruction. SWAPGS exchanges the CPL 0 data pointer from the IA32_KERNEL_GS_BASE MSR with the GS base register. The kernel can then use the GS prefix on normal memory references to access kernel data structures. Similarly, when the OS kernel is entered using an interrupt or exception (where the kernel stack is already set up), SWAPGS can be used to quickly get a pointer to the kernel data structures.

The IA32_KERNEL_GS_BASE MSR itself is only accessible using RDMSR/WRMSR instructions. Those instructions are only accessible at privilege level 0. The WRMSR instruction ensures that the IA32_KERNEL_GS_BASE MSR contains a canonical address.

Operation

IF CS.L ≠ 1 (* Not in 64-Bit Mode *)
    THEN
        #UD; FI;
IF CPL ≠ 0
    THEN #GP(0); FI;
tmp ← GS.base;
GS.base ← IA32_KERNEL_GS_BASE;
IA32_KERNEL_GS_BASE ← tmp;

Flags Affected

None

Protected Mode Exceptions

If Mode ≠ 64-Bit.

#UD

Real-Address Mode Exceptions

If Mode ≠ 64-Bit.

#UD

Virtual-8086 Mode Exceptions

If Mode ≠ 64-Bit.

#UD

Compatibility Mode Exceptions

If Mode ≠ 64-Bit.

#UD

64-Bit Mode Exceptions

If CPL ≠ 0.

#GP(0) If the LOCK prefix is used.

Source: Intel® Architecture Software Developer's Manual (JULY 2017)
Generated: 22-aug-2017: 11:37:19

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