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XADD
XADD — Exchange and Add
| Opcode | Instruction | Op/ En | 64-Bit Mode | Compat/ Leg Mode | Description |
| 0F C0 /r | XADD r/m8, r8 | MR | Valid | Valid | Exchange r8 and r/m8; load sum into r/m8. |
| REX + 0F C0 /r | XADD r/m8*, r8* | MR | Valid | N.E. | Exchange r8 and r/m8; load sum into r/m8. |
| 0F C1 /r | XADD r/m16, r16 | MR | Valid | Valid | Exchange r16 and r/m16; load sum into r/m16. |
| 0F C1 /r | XADD r/m32, r32 | MR | Valid | Valid | Exchange r32 and r/m32; load sum into r/m32. |
| REX.W + 0F C1 /r | XADD r/m64, r64 | MR | Valid | N.E. | Exchange r64 and r/m64; load sum into r/m64. |
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| MR | ModRM:r/m (r, w) | ModRM:reg (r, w) | NA | NA |
Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum of the two values into the destination operand. The destination operand can be a register or a memory location; the source operand is a register.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
IA-32 processors earlier than the Intel486 processor do not recognize this instruction. If this instruction is used, you should provide an equivalent code sequence that runs on earlier processors.
TEMP ← SRC + DEST;
SRC ← DEST;
DEST ← TEMP;The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination operand.
#GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory operand.
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.
#UD If the LOCK prefix is used but the destination is not a memory operand.
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#UD If the LOCK prefix is used but the destination is not a memory operand.
Same exceptions as in protected mode.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory operand.
Source: Intel® Architecture Software Developer's Manual (May 2018)
Generated: 5-6-2018